Agilent Technologies 16700 SERIES LOGIC ANALYSIS SYSTEM 16700 Manuale Utente Scaricare il pdf (Pagina 6)

6

Reference Signal for

Data Alignment

Aligning seemingly unrelated data

sets can be difficult. The operation of

trigger out and trigger in is depend-

ent on the trigger mode of the Xilinx

ILA (extended or basic). There is

also a latency from the Agilent analy-

sis module trigger and the output

port signal. A simple solution is to

find a common data transition

between the ILA and the 16752A data

sets. The trigger out from the ILA is

an ideal signal for this purpose.

This signal is controlled by the Xilinx

ILA, and can be simultaneously

probed by the 16700 Series system

and the ILA. The trigger-out signal

from the ILA might not be identifi-

able from the Verilog source code.

The ILA and ICON modules are

macros that are not compiled, but

instead inserted during FPGA imple-

mentation. They are treated as black

boxes by the synthesis tools.

If you are using an ICON module

compiled for a single ILA, then con-

trol_bus[14] is the external trigger-

out signal. Otherwise, you will need

to probe the external trigger-out sig-

nal using the ILA functions in the

FPGA editor.

We have named the external trigger

out from the Xilinx analyzer "agi-

lent_corr_ref" to identify this special

signal when working with combined

waveforms.

Export the ChipScope Data to FBDF

The interface between the Xilinx

ChipScope and Agilent 16700 Series

logic analysis system is through an

Agilent Technologies Fast Binary

Data Format (FBDF) file. The

ChipScope tool can export its wave-

form directly to FBDF from the file

menu.

Figure 11. Export FBDF file from ChipScope

The Agilent 16700 Series system can

share a drive for Windows

®

use. This

allows the user to directly export

FBDF files to the Agilent 16700

Series system. If sharing is not possi-

ble, the file can be transferred to the

16700 Series system via FTP or a

floppy disk.

Figure 10. Xilinx ChipScope after complete measurement

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