Agilent Technologies U7242A Manuale Utente

Signal IntegrityAnforderungen und Prinzipien an die High-Speed Signal-ÜbertragungIhr Spezialist für Mess- und Prüfgeräte

Bit Error Ratio Testers (BERTs)86100D Infiniium DCA-XAgilent’s Signal Integrity SolutionsAdvanced Design SystemInfiniium 90000 X-Series ENA-TDRN1930B

© 2014 dataTec GmbH | Ferdinand-Lassalle-Str. 52 | D-72770 Reutlingen 11Was ist LVDS?- Schnittstellenstandard nach ANSI/TIA/EIA-644-1995- Differen

Signal Conditioning BasicsTX RXChannelSource Signal• Modify signal to anticipate high-frequency lossReceived Signal• Post-process signal to estimate r

Signal Conditioning – The 3 E’sEmphasis:• Pre-emphasis• De-emphasisEqualization:• Passive (Linear Feedforward Eq.)• Active (Decision Feedback Eq.)Embe

The Reality Is That FR4 Limits Your OptionsFR4 is common, low cost and easy to manufactureBUT it has problems:• Reflections at high speeds• Dispersion

Typical Digital Development Process• Accurate Models• Accurate Simulations• Hardware & Software CorrelationInterconnect DesignSystemDesignActive S

Building SI Expertise Through MeasurementsQuantify Impedance IssuesMake Better MeasurementsWith Quality ProbingUnderstand JitterDevelop an SI Expert/L

Anticipate Problems, Then Fix ThemDevelop Interconnect ModelsSimulate With InterconnectsCreate More AccurateModels And SimulationsDo Jitter Stress Tes

Interconnect Modeling & Simulation• Differential Measurements:• TDR for first order model• VNA for higher accuracy• PLTS for automated calibration

Probing Methods for Differential Signals • InfiniiMax Active Differential Probes• 13 GHz Solder-in, Socket, Browser, SMA, ZIF• Differential or Single-

© 2014 dataTec GmbH | Ferdinand-Lassalle-Str. 52 | D-72770 Reutlingen 2Agenda Was ist Signal Integrity und warum ist es notwendig? Welche Effekt

Active Signal Characterization• Signal Acquisition:• Clock Recovery for embedded clocks• Trigger mechanism for unique events or patterns • Measurement

Functional Validation• Debug Analysis:• EyeFinder and EyeScan to trigger on desired system event• Find parametric, timing and protocol violations • Pr

A Digital system: Serial Data LinkDieBonding wire/pinsPc transmission lineStandard connectorPc transmission lineCableStandard connectorBonding wire/pi

Measurement PlaneDeviceTest CablesStandard ConnectorTest Access Fixture

Measuring Waveforms on a System50ΩWhat you want to Do…What you End up Having…MMT-linecable0 lengthRealtime Oscilloscope= Waveform Analyzer1 meter or m

Simulating an Additional Channel ElementStandard Cable ModelSRealtime Oscilloscope= Waveform Analyzer50Ω Instrument TerminationWhat you Want…What you

Virtual Probing (or Measurement Plane Relocation)50ΩMWaveform AnalyzerSConnectorFixtureCableConnectorFixtureCableRealtime Oscilloscope= Waveform Analy

Virtual Probing (or Measurement Plane Relocation)What you Have…What you Want…MSConnectorBackPlaneConnectorConnectorBack PlaneConnectorHigh Z Probe50ΩD

Modeling your systemCircuit Elements: capacitors, inductors, resistorsParameters: Z, Y, S-ParametersTime Domain: Impulse ResponseFrequency Domain: Tra

How a Source might be modeled:Bond WiresCPadT-linepcbT-lineconnectorKCoup1KCoup2CConZ0Z0LLLL

Signal IntegrityJune 2010Challenges In Digital Design Today• Higher Data Rates Are Causing Signal Integrity (SI) Problems:• Need to include high-frequ

Creating models in ADS (Agilent Design System)S2PSNP5File="SmaCblRsnbrger1701.s2p"21RefS2PSNP4File="SmaCblRsnbrger1701.s2p"21RefS4

S-Parameters: DefinitionS11S21S12S22a1b1b2a222212122121111212221121121aSaSbaSaSbaaSSSSbb+=+==• A Matrix of S-Parameters is use

S-Parameters: Time Domain ViewDeviceTDR TxTDR RxTDR RxTDT: Time DomainTransmissionTDR: Time DomainReflection1 2Evaluate Wave Reflected at Port 1 vs Wa

S-Parameters: Frequency Domain ViewDevice1 2ACBDVector Network AnalyzerSinusoidal StimulusDirectional Devices Pick off voltage waves A, B, C, D•S21

S-Parameters: 4-PortS11S21S34S22a1b1b2a2S33S12S43S44a3b3b4a4S23S32S41S14S13S31S42S24=43214321444342413433323

Transfer Functions• A Transfer Function describes the ratio of a voltage waveentering/exiting one port to a voltage wave exiting/enteringanother port.

Transfer Functions, continuedB1250ΩMSA12DeviceMeasurement PlaneSimulated Measurement PlaneVSM* H (s) = SM(k) * H(n-k) = S(n)Acquisition DataSimulate

Removal of a FixtureA12VSMS

Removal of a Fixture (Waveform After Fixture, no De-Embedding)A12VSM

Before and After ResultsA12VSMSVSM

Data Rates Of Key Serial I/O Technologies0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Go as Detailed as you need

Equalization

Serial systemTransmitterChannelBackplane, short/long cable, board trace.Causing Inter-symbol interference (ISI), loss, reflections, cross-talk.Receive

Transmitter De-emphasisDe-emphasis on, measured at receiverDe-emphasis off, measured at receiverDe-emphasis on, measured at transmitter• We can accoun

Key measure is eye qualityUnequalized 1Gb/s Unequalized 3Gb/sUnequalized 8Gb/sUnequalized 5Gb/s

Feed-Forward EqualizationDelay DelayDelayr(n)r(n)r(n)r(n) r(nr(nr(nr(n----1)1)1)1) r(nr(nr(nr(n----2)2)2)2)╳╳╳╳╳╳╳╳╳╳╳╳ ╳╳╳╳r(nr(nr(nr(n----(N(N(N(N--

−−=∑=NkkknsTapnrAne1)()()()(Decision Feedback EqualizationDelay Delay Delays(n)s(n)s(n)s(n) s(ns(ns(ns(n----1)1)1)1) s(ns(ns(ns(n----2)2)2)2)╳╳╳

FFE vs DFE• FFE implemented in hardware via analog filtering.• All devices perform the same filtering. Fixed in hardware.• DFE is adaptive and is perf

FFE Results1Gb/s 3Gb/s5Gb/s 8Gb/s

Comparison of Results: 8Gb/s•Unequalized: upper left•FFE: upper right• 2 taps• Eye width of 1/3•DFE: lower right• 3 taps• Eye width of 0

What Is Signal Integrity?driverreceiverSeries termination (~40 Ohms)3” PCB TraceSignal Integrity = Where the electrical properties of the interconnect

© 2014 dataTec – Ihr Spezialist für Mess- und PrüfgeräteAgilent Digital Standardisierungsprogramm50Mobile Computing Program• Lead: Thomas GoetzlProg

USB 2.0 OverviewThe USB-IF combined all USB 1.1 and 2.0 speed buses into the USB 2.0 specification USB 2.0 consists of 3 modes--Data Rates Rise Time

USB 2.0 OverviewSignal Level TransferFull/Low Speed3.3V, 12 / 1.5Mbps High Speed 400mV, 480MbpsSignal BandwidthBW = 0.35/Tr= ~1 GHz(Tr= ~400 ps)Sco

© 2014 dataTec – Ihr Spezialist für Mess- und PrüfgeräteUSB 3.0/2.0 – Gesamt-Lösung53Receiver TestTransmitter TestInterconnect TestN5990A Automatic

What is different for USB 3.0USB 2.0 High-Speed 480Mbps NRZI, Half Duplex(1 bi-directional link) 4 signals Dp, DmVCC, GND Cable Lmax= 5meter Icon

Typical USB 3.0 Communication SystemUSB 3.0 DeviceSuperSpeedNon-SuperSpeedRXTXTXRXUSB 3.0 HostSuperSpeedNon-SuperSpeedRXTXRXTXD+D-D+D-SSRX+SSRX-SSRX+S

-or- -or-SuperSpeed Communication – Physical Layer FocusSuperSpeedNon-SuperSpeedSuperSpeedNon-SuperSpeedTXTXRXRXTXRXTX RXRXTXPoint to point communicat

-or-SuperSpeedNon-SuperSpeedRXTXTXRX-or-SuperSpeedNon-SuperSpeedTXRXTXRXPhysical Layer Test SolutionsTrans-mitter(TX)Receiver(RX)Channel / Cable• Agil

What‘s new at USB 3.0?

Typical SuperSpeed Link Turn-on SequenceLTSSM states:Power-upComplianceRx.Detect.ResetRx.Detect.ActiveRx.Detect.ResetRx.Detect.ActivePolling.LFPSPolli

Four Signal Integrity Problems And Their Causes1. Poor signal quality of one net: reflections and distortions from impedance discontinuities in the si

SuperSpeed Measurement RequirementsTransmitter Compliance Testing:Compliance will be measured at the end of the “compliance channel”Use compliance p

USB 3.0 Test fixtureSupport for Tx and Rx Testing– SMA edge launch terminations– SS A and SS B for host, device or cross hub testing

ValiFrame (BitifEye) SW• Uniting all instruments and software seamlessly with one user interface.• Automating all tests required for certification to

BroadR-Reach FixtureMFG by Agilent TechnologiesFixture Supports…Automotive BroadR-Reach spec10/100/1000 Ethernet compliance specKit Includes:- Fixture

BroadR-Reach Transmitter Tests• Transmitter Output Droop Testo Positive Droop Testo Negative Droop Test• Transmitter Timing Jittero Slave Jitter Testo

New EEE tests covering 10/100/1000 Base-TTest coverage as per Energy Efficient Ethernet Test Specification (802.3az-2010) for 10/100/1000BT.Consists o

Fixtures & KitMFG by Wilder TechnologiesFixture Supports…• 10BTe• 100BTe• 1000BTe• Exclusive Licensed Agilent PartKit Includes:- Fixture- 2 – Ethe

© 2014 dataTec – Ihr Spezialist für Mess- und PrüfgerätePCI Express® 3.0 – Total Solution67Receiver TestTransmitter TestInterconnect TestProtocol Te

PCIe 2.0 Fixture Strategy•Fixtures are standardized by the PCI-SIG– Available from the PCI-SIG directly– Used for motherboard and add-in card Testing•

PCIe Gen2 Technology ComparisonItem Gen 2 Gen 1Data Rate 5GT/s 2.5GT/sUnit Interval 200ps 400 psDe-emphasis level -3.5dB & -6dB -3.5dBLane Width x

Addressing High Frequency Effects• Common Design Approaches:• Use signal conditioning • Minimize trace lengths• Impedance matching• Use different mate

PCIe Gen2 Test Flow Model : Add-In Card Tests 1-port (Data) input CH1 CH3Data+-PCIe CBB Use Sigtest for measurement results  No Eye Diagram

Electrical Validation of TransmittersPCIe Validation for PC devicesMotherboard TestingAdd-in Card TestingPCI-SIG AIC Test Fixture (CBB2)PCI-SIG System

PCI Express 3.0 Specification Changes• New 12GHz oscilloscope maximum bandwidth specification• De-embedding required (pin is reference for TX testing)

TX Measurement Challenges for PCIe 3.04.3.3.1.2. Measurement Setup for 8.0 GT/s Transmitters• The PCIe electrical specification references all measure

Signal Path FlowEQ+-ConnectorTP0 TP1ChannelConnectorEQ+-TP2 TP3 TP4TxpTxn RxnRxpTx RxSignal generated hereExits IC hereExits board hereCombine measure

Obtaining S-21TP1SMA connectorRogers PCBPHY chip~5cmAgilent N5230B-245 20GHzVector Network AnalyzerUse SMA’s when AvailableMay require special probing

Transmitter FIR{ 1,0,1} { 1,0,1} and 1n m n nn nTX PKc d cV V−= − = −= =∑ ∑1UI delay1UI delayC-1C0C1dm{-1,1}VTX

Controlling TransmitterAt boot Tx is set by firmware to an appropriate preset• Tx presets include one tap each of preshoot and de-emphasis – Total of

PCI Express 3.0 Electrical Test PlansRequired receiver test at 8.0 GT/s and 5.0 GT/sLink equalization handshaking• Required TX adjustments• Requesting

PCIe Rev. 3.0 Receiver Test Challenges Key new capabilities for PCIe 3.0: Pattern Generator: • Compliant and built-in jitter injection SJ, filtered R

Change Design Methodology For Success• First Sign of SI Problems – Fire Fight Mode• Rely on rules of thumb• Focus on the main effects• Scramble when d

PCIe 3.0 Receiver Test Set-Up from Agilent Replica channelCal. channelTP4 TP5 TP6TP1-20 dB, -12 dB, -2.5 dB loss at 4 GHzRXDUTN4916B de-emphasisJ-BERT

© 2013 dataTec – Ihr Spezialist für Mess- und PrüfgeräteWas ist User Defined Application (UDA)?81User Defined Application Is:A customizable way for

VIELEN DANKFÜR IHREAUFMERKSAMKEIT.

Agilent’s Signal Integrity Solutions