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N4960A Controller Specifications

Agilent N4960A Serial BERT 32 and 17 Gb/s

Agilent N4951A Agilent N4952A

Standalone clock source and/or Serial BERT controller

Clock output configuration: Jitter (stressed), Delay, and Divided outputs available. Clock generator Jitter and Delay outputs are shared with

Pattern Generator (PG) and Error Detector (ED) heads respectively. The PG/ED data rate is double the frequency

of the clock outputs.

Frequency range 1.5 to 16 GHz (1.5 to 8.5 GHz when N4951A-P17, N4951B-H17/D17 or N4952A-E17 is attached)

Outputs Jitter (stressed), Delay, and Divided

Output configuration (all outputs) Differential

Clock output amplitude range 300 mV to 1.7 V pp, single ended

Delayed clock delay range 0 to ±1,000 UI

Divided clock divide ratio ÷ 1, 2, 3,…, 99,999,999 integer divider

Jitter clock injection

- Sinusoidal SJ1, SJ2 1 – 200 MHz, up to 1UI

- Random RJ Up to 75 mUI

- Periodic PJ 1 to 17 MHz, up to 100 UI (to 62.5 kHz)

SJ2, RJ requires Option –CJ1. The amplitude of any stress appearing on the front panel jitter clock output will be 1/2 of the value appearing in the N4951A/B pattern

generator head. Changing stress amplitudes on the front panel jitter clock output will also change the level appearing on the pattern generator output.

Spread spectrum clock (Option -CJ1) 1 Hz to 50 kHz, 0 to 1.0 %, Triangle, down spread, center spread, or up spread.

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 39 40

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