
Digital Delta-t Accuracy (non-Vernier settings)
Same Channel
± 0.01% reading ± 0.1% screen
width ± (1 digital sample period,
2.5 or 5 ns based on sample rate
of 200/400 MSa/s)
Example:
for signal with pulse
width of 10 µs, scope set to
5 µs/div (50 µs screen width), and
single pod active (400 MSa/s),
delta-t accuracy= ±{.01%(10 µs) +
0.1% (50 µs) + 2.5 ns} = 53.5 ns
Channel-to-Channel
± 0.01% reading ± 0.2% screen
width ± (1 logic sample period,
2.5 or 5 ns) ± chan-to-chan skew
(2 ns typical, 3 ns maximum)
Delay Jitter
10 ppm
RMS Jitter
0.025% screen width + 100 ps
Modes
Main, Delayed, Roll, XY
XY
Bandwidth
Max bandwidth
Phase error @ 1 MHz
1.8 degrees
Trigger System:
Sources:
54621A/622A
Ch 1, 2, line, ext
54621D/622D
Ch 1, 2, line, ext, D15 – D0
54624A
Ch 1, 2, 3, 4, line, ext
Modes
Auto, Auto level, Triggered
(normal), Single
Holdoff Time
~60 ns to 10 seconds
Selections
Edge, Pattern, Pulse Width, TV,
Sequence, I
2
C, Duration
Edge
Trigger on a rising or falling edge of
any source.
Pattern
Trigger on a pattern of high, low,
and don’t care levels and a rising
or falling edge established across
any of the sources. The analog
channel’s high or low level is
defined by that channel’s trigger
level.
Pulse Width
Trigger when a positive- or
negative-going pulse is less than,
greater than, or within a specified
range on any of the source
channels.
Minimum pulse width setting
5 ns
Maximum pulse width setting
10 s
TV
Trigger on any scope channel for
NTSC, PAL, PAL-M, or SECAM
broadcast standards on either
positive or negative composite
video signals. Modes supported
include Field 1, Field 2, or both,
all lines, or any line within a field.
Also supports triggering on non-
interlaced fields. TV trigger
sensitivity: 0.5 division of synch
signal.
Sequence
Find event A, trigger on event B,
with option to reset on event C or
time delay.
I
2
C
Trigger on I
2
C (Inter-IC bus) serial
protocol at a start/stop condition or
user defined frame with address
and/or data values.
Duration
Trigger on a multi-channel pattern
whose time duration is less than a
value, greater than a value, greater
than a time value with a timeout
value, or inside or outside of a set
of time values.
Minimum duration setting:
5 ns
Maximum duration setting:
10 s
Autoscale
Finds and displays all active analog
and digital channels (for
54621D/54622D), sets edge trigger
mode on highest numbered
channel, sets vertical sensitivity on
analog channels and thresholds on
digital channels, time base to
display ~1.8 periods. Requires
minimum voltage > 10 mVpp, 0.5%
duty cycle and minimum frequency
> 50 Hz.
Analog Channel Triggering:
Range (Internal)
± 6 div
Sensitivity*
Greater of 0.35 div or 2.5 mV
Coupling
ac (~3.5 Hz), dc, noise reject, HF
reject and LF reject (~ 50 kHz)
Digital (D15 – D0) Channel Triggering
(54621D and 54622D):
Threshold Range (used defined)
±8.0 V in 10 mV increments
Threshold Accuracy*
± (100 mV + 3% of threshold setting)
Predefined Thresholds
TTL = 1.4 V, CMOS = 2.5 V,
ECL = -1.3 V
External (EXT) Triggering:
Input Resistance
1 MΩ, ±3%
Input Impedance
~ 14 pF
Maximum Input
CAT I 300 Vrms, 400 Vpk
CAT II 100 Vrms, 400 Vpk
with 10074C 10:1 probe:
CAT I 500 Vpk, CAT II 400 Vpk
Range
± 10 V
Sensitivity
dc to 25 MHz, < 75 mV
25 MHz to max bandwidth,
< 150 mV
Coupling
ac (~ 3.5 Hz), dc, noise reject,
HF reject and LF reject (~ 50 kHz)
Display System
Display
7-inch raster monochrome CRT
Throughput of Analog Channels
25 million gray scale vectors/sec
per channel
Resolution
255 vertical by 1000 horizontal
points (waveform area)
32 levels of gray scale
High-performance custom graphics display
processor
400 MB/sec graphics BW / channel
2 MB SGRAM (HP 54621A/D and
54622A/D)
4 MB SGRAM (HP 54624A)
9
Performance Characteristics
* Denotes Warranted Specifications, all others are typical. Specifications are valid after a 30-minute warm-up period and ± 10°C from firmware
calibration temperature.
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