2
Specifications
Specifications describe the instrument’s warranted performance. Non-warranted values are described
as typical. All specifications apply after a 30 minute warm-up phase with 50
Ω
source/load resistance
and separate channels. All specifications are valid from 0
°
C to 55
°
C ambient temperature.
Timing Characteristics
Measured at 50% amplitude at fastest transitions in continuous mode and 50 Ω source impedance.
Burst count: 2 to 65536 (single
or double pulses).
Delay: delay, phase, or % of
period.
Double pulse and delay:
mutually exclusive.
Duty cycle: set between 0.1%
and 95% (subject to width limits.
99.9% with overprogramming).
Transition times: leading/
trailing edge or % of width.
Mainframe HP 81104A HP 81110A HP 81110A
Output module HP 81105A HP 81111A HP 81112A
Frequency range 1 mHz to 80 MHz 1 mHz to 165 MHz 1 mHz to 330 MHz
from 1 K
Ω
[1]
Up to 50 MHz typ. Up to 60 MHz typ. N/A
Timing resolution 3.5 digits, 5 ps best case
RMS jitter (period, width, delay)
With PLL
±
0.001%
±
15 ps
With VCO
[2]
±
0.01%
±
15 ps
Period range 12.5 ns to 999.5 s 6.06 ns to 999.5 s 3.03 ns to 999.5 s
Accuracy with PLL
±
0.01% (
±
5%)
[2]
±
0.01% (
±
0.5% typ. after self-cal.,
±
3% without self-cal.)
[2]
Width range 6.25 ns to (period - 6.25 ns) 3.03 ns to (period - 3.03 ns) 1.515 ns to (period - 1.515 ns)
Accuracy
±
5%
±
250 ps
±
0.5%
±
250 ps typ.
[3]
±
3%
±
250 ps
[4]
Add. variable delay range
[5]
0 ns to (period - 12.5 ns) 0 ns to (period - 3.03 ns)
Accuracy
[6]
±
5%
±
0.5 ns
±
0.5%
±
0.5 ns typ.
[3]
±
3%
±
0.5 ns
[4]
Double pulse delay range (width + 6.25 ns) to (width + 3.03 ns) to (width + 1.5 ns) to
(period - width - 6.25 ns) (period - width - 3.03 ns) (period - width - 1.5 ns)
Min. period 25 ns (40 MHz) typ. 12.2 ns (82 MHz) typ. 6.06 ns (165 MHz) typ.
Accuracy
±
5%
±
250 ps
±
0.5%
±
150 ps typ.
[3]
±
3%
±
150 ps
[4]
Transition time range (10/90) 3 ns to 200 ms variable 2 ns to 200 ms variable 0.8 ns or 1.6 ns selectable
Minimum (with overprogramming)
≤
3 ns
≤
2 ns/1.4 ns typ. for
≤
600 ps for Vpp
≤
1 V
ECL levels (20/80) 450 ps typ. for
5 ns typ. for 1 K
Ω
source ECL levels (20/80)
imped.
≤
900 ps for Vpp > 1 V
Accuracy
±
10%
±
200 ps
Linearity 3% typ. for transitions > 100 ns N/A
Notes:
[1] Source impedance is selectable from 50 Ω or 1 KΩ for the HP 81105A and HP 81111A.
[2] If the startable oscillator (VCO) is used (PLL not active).
[3] After self-calibration.
[4] Without self-calibration.
[5] 0 ns to (period - 17.6 ns) in ext. width mode.
[6] Changing of amplitude may add 0.5 ns.
Leading and trailing edges are
independent (HP 81111A/
HP 81105A) within one of the
following overlapping segments
(1:20 ratio): 2 ns (3 ns) - 20 ns,
10 ns - 200 ns, 100 ns - 2 ms,
1 µs - 20 µs, 10 µs - 200 µs,
100 µs - 2 ms, 1 ms - 20 ms,
10 ms - 200 ms.
Output timing fidelity: period,
delay, and width are continuously
variable without any output
glitches or dropouts.
Repeatability: is typ. four times
better than accuracy.
Overprogramming: all
parameters of the HP 81110A,
except transitions, can be set to
whatever the 330 MHz timing
system will allow. This applies
also when the HP 81111A output
module is used.
(28 pagine)
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