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Test 2-2: Leakage

Test

The test verifies the input impedance by measuring the voltage drop across a

known resistor in series with the input impedance. Leakage is measured

from HI to LO, HI to Chassis, and LO to Chassis. Because of the solid state

nature of the switches and input protection, the leakage is measured at both

+10 Vdc and -10 Vdc.

HI to LO Leakage 1. Make Hardware Connections

• Turn power supply, DMM, and mainframe power OFF

• Connect DMM, power supply, and resistor as shown in Figure

2-6

• Turn power supply, DMM, and mainframe power ON

• Set power supply output to +10 Vdc ± 0.1 Vdc

2. Check Direct Terminals Leakage

• Send *RST to FET Multiplexer

• Send TRIG SGL to DMM

• Record the DMM reading in Table 2-1

Positive Polarity, HI to LO, Direct

• The DMM measurement should be less than 0.010 Vdc. A

measurement out of this range indicates a failure of the FET

Multiplexer and troubleshooting/repair/replacement procedures,

described in Chapter 4, should be performed before proceeding

with Test 2-2

Agilent E1300B/E1301B

Figure 2-6. Positive HI to LO Leakage Connections

2-12 Verification Tests

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Agilent Technologies E1356A Manuale di Servizio Pagina 30