Agilent Technologies 86100D Manuale Utente Pagina 19

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Clock recovery 86108A 86108B-216 86108B-232
Data rate input range (Continuous tuning) 0.05 to 14.2 Gb/s (requires
FW revision 8.1 or higher)
0.05 to 16 Gb/s 0.05 to 32 Gb/s
Clock frequency input range (Continuous
tuning)
0.025 to 6.75 GHz 0.025 to 8 GHz 0.025 to 16 GHz
Minimum input level to aquire lock 175 mV
pp
175 mV
pp
175 mV
pp
Recovered clock random jitter
(used as internal trigger)
1
Internal recovered clock
trigger
< 500 fs at 2 Gb/s
< 400 fs at 5 and 10 Gb/s
< 350 fs at data rate < 2 Gb/s
< 300 fs at data rate ≥ 2 Gb/s
< 350 fs at data rate < 2 Gb/s
< 300 fs at data rate ≥ 2 Gb/s
Clock recovery adjustable loop
bandwidth range (user selectable)
0.015 to 10 MHz 0.015 to 20 MHz 0.015 to 20 MHz
Clock recovery loop peaking range Up to 4 settings (dependent on loop BW)
Loop bandwidth accuracy ±30%
Tracking range
(includes spread spectrum tracking)
±2500 ppm ±0.25%
Aquisition range
±5000 ppm
Maximum consecutive identical digits to lock 150
Auto relocking If signal lock is lost, system can automatically attempt to regain phase-lock.
User selectable to enable/disable
Residual spread spectrum
–72 ±3 dB @ 33 kHz –84 ±3 dB @ 33 kHz –84 ±3 dB @ 33 kHz
Front panel recovered clock amplitude
0.15 to 1.0 Vpp (0.3 to 1.0 Vpp)
Front panel recovered clock divide
ratio (user selectable)
1, 2, 4, 8, 16
2, 4, 8, 16
1, 2, 4, 8, 16
2, 4, 8, 16
1, 2, 4, 8, 16
2, 4, 8, 16
Recovered clock front panel
connector type
SMA
Internal frequency counter accuracy ±10 ppm
1. These values indicate performance with the internal precision timebase disabled. With precision timebase enabled, system jitter performance is dramatically decreased.
See page 7.
Modules specifications
dual electrical
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