
81133A/81134A Performance Test Report
Page 2 of 5
Delay (Output 1)
TR
Entry
Test Limit
Min.
Actual Limit
Max.
Pass/Fail
∆t
o
3-1
3-2
3-3
0.00 ns
1.00 ns
1.50 ns
2.00 ns
N/A
980 ps
1.48 ns
1.98 ns
____________
Fixed Delay
1.02 ns
1.52 ns
2.02 ns
Pass Fail
Pass Fail
Pass Fail
Delay (Output 2) only for 81134A
TR
Entry
Test Limit
Min.
Actual Limit
Max.
Pass/Fail
∆t
o
3-1
3-2
3-3
0.00 ns
1.00 ns
1.50 ns
2.00 ns
N/A
980 ps
1.48 ns
1.98 ns
____________
Fixed Delay
1.02 ns
1.52 ns
2.02 ns
Pass Fail
Pass Fail
Pass Fail
Clock Jitter (Output 1)
TR
Entry
Test Limit
Min.
Actual Limit
Max.
Pass/Fail
4-1
4-2
4-3
4-4
100 MHz
1.0 GHz
2.0 GHz
3.0 GHz
N/A
N/A
N/A
N/A
____________
____________
4 ps RMS
4 ps RMS
4 ps RMS
4 ps RMS
Pass Fail
Pass Fail
Pass Fail
Pass Fail
Data Jitter (Output 1)
TR
Entry
Test Limit
Min.
Actual Limit
Max.
Pass/Fail
4-5
4-6
4-7
4-8
100 MHz
1.0 GHz
2.0 GHz
3.0 GHz
N/A
N/A
N/A
N/A
____________
____________
5 ps RMS
5 ps RMS
5 ps RMS
5 ps RMS
Pass Fail
Pass Fail
Pass Fail
Pass Fail
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