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Logic Analyzer

Specifications

The following specifications are the performance standards or limits against which

the HP 1650B/51B Logic Analyzer is tested.

Probes Minimum Swing: 600 mV peak-to-peak.

Threshold Accuracy:

Voltage Range Accuracy

-2.0V to + 2.0V

150 mV

-9.9V to -2.1V

300 mV

+ 2.1V to + 9.9V

300 mV

State Mode Clock Repetition Rate: Single phase is 35 MHz maximum. With time or state

counting, minimum time between states is 60 ns (16.67 MHz). Both mixed and

demultiplexed clocking use master-slave clock timing; master clock must follow

slave clock by at least 10 ns and precede the next slave clock by

50 ns.

Clock Pulse Width:

10 ns at threshold.

Setup Time: Data must be present prior to clock transition,

10 ns.

Hold Time: Data must be present after rising clock transition; 0 ns.

Data must be present after falling clock transition, 0 ns (HP 1651B); data must be

present after falling L clock transition, 0 ns (HP 1650B); data must be present after

falling J, K, M, and N clock transition, 1 ns (HP 1650B).

Timing Mode Minimum Detectable Glitch: 5 ns wide at the threshold.

General Information HP 1650B/1651B

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Agilent Technologies 54502A Manuale di Servizio Pagina 15