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6. Press RUN. The State Listing is displayed and shows alternating Fs and 0s

for the channels under test as in figure 3-20.

Note To ensure consistent pattern of alternating Fs and 0s, use the front-panel ROLL

keys and knob to scroll through State Listing.

7. Connect the next clock to the test connector and repeat steps 4 and 6.

Repeat until all clocks have been tested (clocks J, K, L, M and N).

8. Remove the probe tip assembly from the logic analyzer probe cable and

attach to the next logic analyzer probe cable to be tested. Take care not to

dislodge grabbers from the test connector.

9. Repeat steps 3, 4, 6 and 7 until all pods have been tested (pods 1 through 5).

Start again with the rising edge of J clock and test the pod with all clocks.

10. Repeat until the lower bits of all pods have been tested (pods 1 through 5).

11. Disconnect lower eight bits (bits 0 through 7) from test connector. Attach

upper eight bits (bits 8 through 15) to the test connector.

12. Repeat steps 3, 4, 6, 7 and 8 until the upper bits of all pods have been tested

(pods 1 through 5).

Figure 3-20. State Listing for Data Test 4

HP 1650B/1651B Performance Tests

Service Manual 3-17

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Agilent Technologies 54502A Manuale di Servizio Pagina 52