
2. Adjust pulse generator for the output in figure 3-19. Pulse generator settings
are different for HP 1650B and HP 1651B.
Setting for HP 8161A:
Parameter Output A Output B
Input Mode Norm ---
Period (PER)
HP 1650B 57 ns ---
HP 1651B 80 ns ---
Width (WID) 20 ns 10 ns
Leading Edge (LEE) 1 ns 1 ns
Trailing Edge (TRE) 1 ns 1 ns
High Level (HIL) 1.9V 1.9V (see Note)
Low Level (LOL) 1.3V 1.3V (see Note)
Delay (DEL)
HP 1650B 18.5 ns ---
HP 1651B 30 ns ---
Double Pulse (DBL)
HP 1650B --- 28.5 ns
HP 1651B --- 40 ns
Output Mode ENABLE ENABLE
Note The voltage levels of the waveforms must have the correct amplitude at the logic
analyzer probe tips. The pulse generator output may have to be increased slightly
to compensate for loading by the logic analyzer.
3. Assign the pod under test to Analyzer 1 in System Configuration as in
previous figure 3-4.
4. In the State Format Specification assign Clock Period < 60 ns, and rising
edge of J clock. Also, assign lower 8 channels of the pod under test to a label
as in previous figure 3-12.
5. Set the State Trace Specification without sequencing levels and set Count
Off as in previous test figure 3-13.
Figure 3-19. Waveform for Data Test 4
Performance Tests HP 1650B/1651B
3-16 Service Manual
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