Agilent Technologies 54502A Manuale di Servizio Scaricare il pdf (Pagina 58)

b. Assign falling clock transition of J clock to Master Clock and rising J

clock transition to Slave Clock.

c. Assign ALL channels to pod under test (only bits 0 through 7 are be

available for assignment).

d. Set Clock Period to < 60 ns.

5. Set State Trace Specification without sequencing levels and set Count Off

as in previous figure 3-13.

6. Press RUN. The State Listing shows alternating Fs and 0s for the pod under

test as in figure 3-28.

Note To ensure consistent pattern of alternating Fs and 0s in listing, use front-panel

ROLL field and knob to scroll through State Listing.

7. Connect the next clock to the test connector and repeat steps 4 and 6.

8. Repeat until all clocks have been tested (clocks J, K, L, M and N).

9. Remove the probe tip assembly from the logic analyzer probe cable and

attach to the next logic analyzer probe cable to be tested. Take care not to

dislodge grabbers from the test connector.

10. Repeat steps 3, 4, 6 and 7 until all pods have been tested (pods 1 through 5).

Start again with the falling edge of J clock as the Master Clock and rising

edge of the J clock as the Slave Clock.

Figure 3-28. State Listing for Data Test 6

HP 1650B/1651B Performance Tests

Service Manual 3-23

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 110 111

Nessun commento

Agilent Technologies 54502A Manuale di Servizio Pagina 58