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Setting for HP 8161A:

Parameter Output A Output B

Input Mode Norm ---

Period (PER) 57 ns ---

Width (WID) 11 ns 10 ns

Leading Edge (LEE) 1 ns 1 ns

Trailing Edge (TRE) 1 ns 1 ns

High Level (HIL) 3.2 V 3.2 V

Low Level (LOL) 0 V 0 V

Delay (DEL) 0 ns ---

Double Pulse (DBL) --- 28.5 ns

Output Mode ENABLE ENABLE

3. Assign the pod under test to Analyzer 1 in the System Configuration as in

previous test figure 3-4.

4. In the State Format Specification menu assign Clock Period < 60 ns, and

falling edge of J clock. Also, assign the lower 8 channels of the pod under test

to a label as in figure 3-12.

5. Set the State Trace Specification without sequencing levels and set Count

Off as in previous figure 3-13.

6. Press RUN. The State Listing is displayed and lists alternating Fs and 0s as

in figure 3-17, if test has passed.

Note To ensure consistent pattern of alternating Fs and 0s, use the front-panel ROLL

field and knob to scroll through State Listing.

7. Connect the next clock to the test connector and repeat steps 4 and 6 for the

appropriate clock. Repeat until the J, K, M and N clocks have been tested.

8. Remove the probe tip assembly from the logic analyzer probe cable and

attach to the next logic analyzer probe cable to be tested. Take care not to

dislodge grabbers from the test connector. Repeat steps 3, 4, 6 and 7 until all

pods have been tested (pods 1 through 5). Start again with the falling edge of

the J clock and test the pod with all clocks except L clock.

Figure 3-17. State Listing for Data Test 3

Performance Tests HP 1650B/1651B

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Agilent Technologies 54502A Manuale di Servizio Pagina 49