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The Loop Suppression Verification

Introduction

Verification of the Phase Lock Loop Suppression insures that the Phase

Lock Loop Bandwidth (PLL BW), the Phase Detector Constant, and the

VCO Tuning Constant are all accurate for the measurement. (Note that the

HP 3048A always corrects for the loop suppression whether verification is

selected or not.)

Description

The HP 3048A verifies Loop Suppression before beginning the measure-

ment by closing the phase lock loop and injecting noise into the loop. The

response of the loop is measured and recorded. The loop is then opened,

and a measurement is made of the open loop response. The suppression of

the PLL is the difference between the closed loop response and open loop

response to the injected noise. The measured Loop Suppression curve is

smoothed and then four points are selected along the curve including the

peak and the — 8 dB point. The measured curve is then compared to the

theoretical curve at the four selected points. Figure 2-16 shows an example

of a Loop Suppression curve measured by the HP 3048A. (For informa-

tion about displaying and interpreting the curve, and using the 11848A

Control softkey for troubleshooting this measurement, refer to Test Mode

in Chapter 5 Special Functions.

The amount of adjustment required to fit the theoretical curve to the mea-

sured curve is recorded as the PLL GAIN CHANGE on the Suppression

Graph and the frequency of the Assumed Pole. The Assumed Pole is a

software controlled term used to fit the Adjusted Theoretical loop response

to the smoothed measured response of the phase lock loop. The MAX ER-

ROR is the final amount of error existing between the adjusted theoretical

curve and the measured curve of the phase lock loop suppression. If the

PLL GAIN CHANGE or MAX ERROR is greater than 1 dB, the System

2-54 Calibr Process: $N w/PLL

rev.05SEP89

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Agilent Technologies HP 8642A/B Specifiche Pagina 123