
Phase Lock Loop Suppression
Configuring the HP 3048A in the Trouble Shoot Mode also causes the
system to display the plot of the PLL Suppression Curve when it is verified
during the measurement calibration, whether an accuracy specification
degradation occurs or not. Note that the PLL Suppression verification must
be defined in the Calibration Process display prior to the measurement in
order for verification to occur. (Refer to Calibration Process in Chapter 2,
Measurement Definitions and Parameter Summary in Chapter 3, Graphic
Functions for details about the PLL Suppression verification.)
THEORETICAL
AND
HCTURL 'LOOP SUPPRESSION' FHCTOPS
+ 10
dB
PLL CAIN CHNG
MAX ERROR
CLOSED
PLL BH
PK TUNE RANGE
ASSUMED POLE
DET. CONSTANT
VCO CONSTANT
bVB.E-3
C5.S6E-:!
67.35
145.5
2.466E+3
261.8E-3
81.13
rlB
CJB
Hz
Hz
Hz
V/Raci
Hz/V
-IB dB
/
L06E-3 1 10
U3Ci
l.E+3
Figure 5-1. HP 3048A Display of the Phase Lock Loop Suppression Curve.
PLL Suppression Parameters
The following measurement parameters are displayed along with the PLL
Suppression Curve.
Test Mode 5-5
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